The present disclosure relates to a semiconductor device such as a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus such as a camera including the solid-state imaging device.
In recent years, miniaturization and multilayering of inner wirings due to high integration of LSI (large-scale integrated circuits) have been proceeding. However, the high cost of a semiconductor manufacturing apparatus due to the miniaturization greatly affects the cost of LSI. In addition, a method which mixes and disposes a logic circuit, memory, an imaging device, or the like on single chip is performed. However, in order to perform the mixing and disposing while keeping process characteristics in each device to the maximum, complication and cost increase of the process may not be able to be avoided.
Under such circumstances, the following method is performed. That is, by bonding and laminating the single function LSIs (a logic circuit, memory, and an imaging element) with a wafer level and a chip level, a single chip is achieved without sacrificing the integration of the LSI having high performance. Consideration with respect to a configuration, which obtains electric conduction between laminated wafers or chips in a via in which insulating films are adhered and penetrated, has also been proceeding. However, when the semiconductor elements are close to each other, problems such as influence of electromagnetic waves generated by operation of mutual elements and crosstalk occur. In addition, malfunction due to heat generated by operation of mutual elements is also a problem.
Particularly, when an imaging element and an image processing element are laminated, problems such as an increase of dark current and increase of white noise in the imaging element due to heat generated by the operation of the image processing element occur. In addition, when a logic circuit (a metal wiring) is disposed under the imaging element, incident light is reflected at a wiring metal layer, the reflected light is returned to a photoelectric conversion region, and a problem which affects imaging performance also occurs.
As a method solving the above-described problems, in Japanese Patent No. 4379295, a configuration in which a conductive metal plate having a penetration electrode is interposed between mutual elements is suggested. However, in the configuration, problems such as an increase in the number of manufacturing steps and increase of the cost, a problem such as difficulty corresponding to miniaturization of the element, or a problem such as difficulty for application to bonding of wafer-to-wafer occur.